1. Technical Field
The present invention relates to an RF frequency synthesizer for wireless communication and a high-speed automatic calibration device for the frequency synthesizer. More particularly, the invention relates to a wideband fractional-N frequency synthesizer and a high-speed automatic calibration device therefor having improved calibration speed and precision.
2. Description of the Related Art
The RF frequency synthesizer is a device for generating signals at a particular frequency and is essential in wireless transceivers.
In such frequency synthesizers, a phase-locked loop (PLL) system is mainly used to generate a wanted target frequency.
In a frequency synthesizer, a wider range of output frequency is very likely to cause greater changes in VCO gain (KVCO) and division ratio N, and therefore phase noise, loop bandwidth (LBW), and lock time is also very likely to vary greatly as the output frequency varies. As such, the wider the bandwidth of a frequency synthesizer, the more difficult it becomes to provide an optimal design. To overcome this problem, it is essential to utilize an automatic calibration circuit, which maintains the loop bandwidth, lock time, and phase noise at a relatively constant level over the wide bands.
FIG. 1 is a schematic illustration of a frequency synthesizer having an automatic frequency calibration circuit according to the related art.
Referring to FIG. 1, a voltage controlled oscillator 100 may include a capacitor bank 102, and an automatic frequency calibration circuit 104 may search for a suitable control code for the capacitor bank 102.
As illustrated in FIG. 1, a frequency synthesizer can include a frequency divider 106, a phase-frequency detector and charge pump 108, and a low-pass loop filter 110.
In a frequency synthesizer such as that shown in FIG. 1, the time spent by the automatic frequency calibration circuit 104 (frequency calibration time) in searching for a control code for the capacitor bank 102 may be a major cause of prolonging the overall lock time of the frequency synthesizer.
As the additional delay for searching the control code may increase power consumption and lower data transmission speed in wireless transceivers, it is an important issue in designing an automatic frequency calibration circuit to reduce the frequency calibration time of the automatic frequency calibration circuit.
Another important issue in designing an automatic frequency calibration circuit is frequency resolution. Frequency resolution is especially important in a fractional-N frequency synthesizer.
FIG. 2 represents frequency tuning curves for a voltage controlled oscillator, where FIG. 2(a) shows typical frequency tuning curves for a fractional-N frequency synthesizer.
As illustrated in FIG. 2(a), there may often be occasions when the frequency spacing between adjacent curves (fspacing) becomes smaller than the frequency (fREF).
In order for the automatic frequency calibration circuit to operate with an acceptable precision, the frequency resolution (fresolution) always has to be kept smaller than the spacing between adjacent curves (fspacing), and this means that the frequency resolution of the automatic frequency calibration circuit has to be smaller than the reference frequency.
This problem can occur not only in a fractional-N frequency synthesizer, but also in a typical integer-N wideband frequency synthesizer.
Referring to FIG. 2(b), it can be noted that, in a wideband frequency synthesizer, the changes in the gain of the voltage controlled oscillator (KVCO(n)) and in the spacing between adjacent curves (fspacing(n)) may increase greatly according to the capacitor bank control code n value.
For example, when using a capacitor bank having a binary weighted structure, the rate of change for fspacing(n) is known to be cubically proportional to the ratio of the maximum to minimum operating frequencies of the voltage controlled oscillator (J. Kim et al., “A Wideband CMOS LC VCO with Linearized Coarse Tuning Characteristics,” IEEE Tran. Circuits and Systems-II: Express Brief, vol. 55, no. 5, pp. 399˜403, May 2008).
In this case, fspacing(n) can become easily smaller than fREF, meaning that the frequency resolution of an automatic frequency calibration circuit has to be designed to be smaller than fREF for a wide band synthesizer design, not only in a fractional-N type but also in an integer-N type frequency synthesizer.
However, for a frequency synthesizer to which a conventional automatic frequency calibration circuit such as that illustrated in FIG. 1 is applied, obtaining a frequency resolution lower than fREF may require a very long calibration time.
A third design issue for an automatic frequency calibration circuit is the calibration method used for the frequency calibration.
An automatic frequency calibration circuit according to the related art may use the method of comparing the frequency (fDIV) of a divided signal of a voltage controlled oscillator with a reference frequency (fREF).
This relative frequency comparison method is currently the most widely used method. It usually provides a frequency calibration speed in the order of several tens of microseconds. With this method, however, two pulses are counted simultaneously, and the relative comparison of the two signal frequencies is performed using a frequency comparator. Here, since the clock speed of the counter is as low as the reference frequency, a relatively long calibration time is required, ranging from about several tens to several hundreds of microseconds, if a high resolution is needed.
Another method is to perform the frequency comparison after converting the frequencies into voltage quantities using a time-to-voltage converter (TVC).
While this method of using a TVC can be very fast, with the frequency calibration time less than a microsecond, when it is applied to a fractional-N frequency synthesizer, additional time may be required to compensate for errors caused by the delta-sigma modulator (DSM), so that the calibration time is lengthened to a similar level to that of other conventional methods.
A second calibration required in a frequency synthesizer is the calibration of loop bandwidth (LBW). As shown in Equation 1 below, the loop bandwidth of a charge pump PLL is proportional to charge pump gain (ICP) and KVCO, and is inversely proportional to the phase-locked loop's division ratio N. Here, since KVCO and N may vary according to the output frequency, the loop bandwidth may also vary accordingly.
                    LBW        ∝                  lcp          ·                                                    Kvco                                                                    N                                                                        [                  Equation          ⁢                                          ⁢          1                ]            
Therefore, in order to keep the loop bandwidth constant, it may be necessary to compensate for the changes in KVCO and N by suitably adjusting the charge pump gain (ICP).
In a phase-locked loop based wideband frequency synthesizer, a binary weighted capacitor bank is generally used. Since KVCO is proportional to
      (          [                        VCO          ⁢                                          ⁢          maximum          ⁢                                          ⁢          frequency                          VCO          ⁢                                          ⁢          maximum          ⁢                                          ⁢          frequency                    )        ]    3in such a phase-locked loop, the loop bandwidth is proportional to
      (          [                                                  VCO              ⁢                                                          ⁢              maximum              ⁢                                                          ⁢              frequency                                                                          VCO              ⁢                                                          ⁢              maximum              ⁢                                                          ⁢              frequency                                          )        ]    2if the charge pump gain (ICP) is kept constant. Therefore, the change in loop bandwidth becomes greater as the operating band becomes wider.
Although many studies have been conducted aimed at keeping the loop bandwidth constant, there have been problems in applying the conventional approaches to the wide band design.
For example, the method of compensating KVCO non-linearity with ICP (C. Lam, et al., “A 2.6-GHz/5.2-GHz Frequency Synthesizer in 0.4-μm CMOS Technology,” IEEE Journal of Solid State Circuits, vol. 35, no. 5, pp. 788˜794, May 2000) is very sensitive to the process, voltage, temperature variations. The method using an averaging varactor to keep KVCO constant and compensating the change in division ratio N with ICP in an analog split-tuned phase-locked loop structure (T. Wu, et al., “Method for Constant Loop Bandwidth in LC-VCO PLL Frequency Synthesizers,” IEEE Journal of Solid State Circuits, vol. 44, no. 2, pp. 427˜435, February 2009) results in poorer phase noise performance due to the use of a large varactor in the phase-locked loop structure. The method of compensating loop bandwidth using step response time in the time domain of a phase-locked loop (Y. Akamine et al., “ΔΣ PLL Transmitter with a Loop-Bandwidth Calibration System,” IEEE Journal of Solid State Circuits, vol. 43, no. 2, pp. 497˜506, February 2008) is sensitive to changes in KVCO and is thus unsuitable for wide band applications.